Memory devices are commonly used to store information (either temporarily or permanently) in a number of applications; particularly, in a non-volatile memory device, the information is preserved even when a power supply is off. For example, in a flash EEPROM the memory cells (typically consisting of floating gate MOS transistors) are arranged in a matrix that is integrated in a common substrate (so as to obtain a very compact structure). However, this may require that all the memory cells of the matrix be erased at the same time; for this purpose a suitable biasing voltage is applied to the common substrate; the common substrate in then discharged so as to be ready for the next operations to be performed on the memory device.
In order to provide a finer granularity of the erase operation, memory devices with a so-called page-flash as word-erasable architecture have been proposed. In this case, the memory cells are partitioned into blocks, which are integrated into corresponding insulating wells (formed in the common substrate); each block contains multiple rows of memory cells (defining corresponding words). As a result, it is possible to erase the memory cells of a single word at a time (by suitably biasing and discharging its insulating well). Typically, the word-erasable flash memories require the application of high biasing voltages (up to 10V) for obtaining acceptable erase times (comparable to the ones of the standard flash memories). These biasing voltages generally exceed the maximum absolute rating allowed by the available technology (i.e., 9V). Therefore, the switching circuits that are necessary to select the desired block are implemented with multiple transistors in a cascade configuration (so as to withstand the above mentioned high biasing voltages).
A problem of the memory devices know in the art is that a relatively large current may flow through the switching circuits (especially during the discharge of the insulating well following the erase operation).
This may cause a significant voltage drop at the multiple transistors of the switching circuits, which voltage drop may impair their correct operation.
Therefore, those transistors often must have a low resistance (to allow discharging the insulating well to the desired value). However, this may require very large transistors with a corresponding waste of area in a chip of semiconductor material where the memory device is integrated.
The problem is particular acute in the word-erasable flash memories, since they have a high number of switching circuits (i.e., one per block).